Integrated circuit field effect transistors are widely used in integrated circuit devices, such as logic, memory and/or processor devices. For example, integrated circuit field effect transistors are widely used in Dynamic Random Access Memory (DRAM) devices. As is well known, a conventional integrated circuit field effect transistor includes spaced apart source and drain regions in an integrated circuit substrate, with an insulated gate electrode therebetween. In operation, a channel is formed in the substrate between the source and drain regions and beneath the insulated gate electrode.
As the integration density of integrated circuit field effect devices continues to increase, the channel length may decrease to submicron dimensions. These short channel devices may create various undesirable short channel effects, such as punch-through. Semiconductor-on-insulator devices have been developed to potentially reduce short channel effects. In contrast with a bulk field effect transistor that is formed in bulk semiconductor, in a semiconductor-on-insulator device the field effect transistor is formed in a semiconductor layer on an insulator layer on a base substrate.
In other attempts to reduce short channel and/or other effects, double-gated field effect transistors have been developed. In a double-gated field effect transistor, a bottom gate and a top gate may be formed on opposite sides of the channel region.
Field effect transistors having projecting regions also have been developed in attempts to reduce short channel and/or other effects. For example, U.S. Pat. No. 5,844,278 to Mizuno et al. describes a “Semiconductor Device Having a Projecting Element Region”, as noted in the Mizuno et al. Title. As noted in the Mizuno et al. Abstract, a semiconductor device includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.